The problem: 4 bits naturally count to 15

Boolflow's CNT4 block counts 0 through 15 before rolling over, because 4 bits give exactly 16 states. Driving a seven-segment display with raw BCD needs a counter that instead counts 0 through 9 and wraps back to 0 — a decade, or BCD, counter.

Detecting 10, not 9

CNT4 has an asynchronous RST input: whenever RST=1, the count clears to 0 immediately, regardless of the clock. The classic trick is to decode the count value 10 (binary 1010 — bits Q3 and Q1 both 1) with a single AND gate and feed that directly into RST. The counter counts normally up through 9, then the instant it reaches 10, RST fires and clears it back to 0 before the next clock edge even arrives.

Why decode 10, and not 9, for the reset

If RST were instead wired to detect 9, the counter would clear itself the moment it reached 9 and a viewer would never actually see 9 displayed. Decoding 10 lets the counter genuinely pass through 9 as a stable, visible state — the count only ever touches 10 for the same near-instant flicker that an asynchronous clear takes to react, invisible in practice. This is exactly the technique classic 7490-style decade-counter chips use internally.

Try it yourself

Wire Q1 AND Q3 from a CNT4 block into its own RST input in the circuit editor, drive the count into a SEG7 display, and confirm the digit cycles 0 through 9 and back to 0 instead of continuing on to 15.