Combinational vs. sequential logic
Everything covered in the other articles — gates, truth tables, Karnaugh maps — describes combinational logic: circuits whose output depends only on the current input. Memory requires something more: sequential logic, where the output also depends on past inputs. Latches and flip-flops are the basic building blocks of sequential logic.
Latches: level-sensitive
An SR latch is the simplest memory element: Set (S=1) forces the output to 1, Reset (R=1) forces it to 0, and S=R=0 holds the previous value. The forbidden state S=R=1 produces an undefined result and must be avoided.
A D latch improves on this: while its Enable signal (E) is high, the output Q continuously follows the data input D. As soon as E goes low, Q freezes at whatever value D had at that instant. This is what "level-sensitive" means — the latch is listening the entire time E is high, not just at one instant.
Flip-flops: edge-triggered
A D flip-flop only samples its input D at the exact moment the clock signal transitions — typically on the rising edge. Between clock edges, the output is completely insensitive to changes on D. This is "edge-triggered" behaviour, and it is what makes flip-flops, not latches, the standard building block for registers, counters, and pipelined processors.
The reason edge-triggering matters: in a level-sensitive latch, any glitch on the input while Enable is high propagates straight through to the output. In a large synchronous circuit with thousands of latches, this leads to race conditions and unpredictable behaviour. Edge-triggered flip-flops, sampled by a single global clock, eliminate that problem by design.
See it in action
Boolflow includes SR latches, D latches, and D flip-flops as ready-made blocks. Load the flip-flop example, toggle the CLOCK element, and watch how the D latch output tracks the input continuously while the D flip-flop output only updates on the clock edge.