Level signals vs. pulses
A button held down for half a second produces a level signal that stays high across dozens of clock cycles. Many circuits — a counter that should advance once per button press, not once per clock cycle the button happens to be held — need that level converted into a pulse: a signal that goes high for exactly one clock cycle at the moment of change, then drops back down regardless of how long the input stays high.
Building one from a flip-flop and an AND gate
The classic edge detector delays the signal by one clock cycle through a D flip-flop, then ANDs the live signal with the inverted, delayed copy:
- Pulse = A · ¬A_prev, where A_prev is A sampled one clock edge ago.
- The moment A rises from 0 to 1, A_prev is still 0 for exactly one cycle, so the AND briefly outputs 1 — precisely one pulse per rising edge, no matter how long A then stays high.
Boolflow's EDGE_DET and FALL_DET
Boolflow ships this circuit pre-built as the EDGE_DET (rising-edge) and FALL_DET (falling-edge) blocks. Feed a held-down INPUT switch through one of them before it reaches a counter's clock input, and the counter advances exactly once per toggle instead of racing ahead every simulation step the input is held high.
The related problem: dividing frequency
A different but related need is generating a slower, regular clock from a faster one rather than a one-shot pulse from a level signal. Boolflow's CLK_DIV block halves a CLOCK signal's frequency each time it's chained, the same toggling behaviour that makes binary counters count in the first place.