Fixed gates vs configurable logic

Every circuit in the other articles is built from gates whose function is fixed at design time — an AND gate can never become an OR gate. An FPGA (Field-Programmable Gate Array) takes the opposite approach: it ships as a grid of generic, reconfigurable logic cells whose behaviour is set after manufacturing, by loading a configuration that tells each cell which function to perform.

The look-up table (LUT)

The core of each reconfigurable cell is a Look-Up Table: storage holding one output bit for every possible combination of its inputs — which is exactly a truth table, stored directly in memory instead of built from gates. A 4-input LUT holds 16 bits, one per row of a 4-variable truth table, and can therefore implement any one of the 65,536 possible 4-input Boolean functions just by changing which 16 bits are stored, with no rewiring at all.

An FPGA as an array of LUTs and flip-flops

A full FPGA combines thousands of these LUTs with flip-flops and a programmable interconnect fabric that wires LUT outputs to other LUTs' inputs, or to flip-flops for state. Loading a "bitstream" configures every LUT's contents and every interconnect switch simultaneously, turning the generic grid into whatever specific circuit was designed — including, in principle, an entire CPU.

Boolflow's PLM blocks

Boolflow's PLM (Programmable Logic Matrix) blocks model exactly this idea at small scale: instead of wiring individual AND/OR/NOT gates, you directly specify the output for each input combination, the same way a LUT's contents are specified. A PLM block with N inputs is functionally identical to an N-input LUT.

From truth table to LUT configuration

Because a LUT or PLM block stores a function rather than building it from gates, the workflow inverts: instead of simplifying with De Morgan's laws or a Karnaugh map to minimize gate count, you write out the desired truth table directly and load it in. Open a PLM element in Boolflow's editor (see the Help reference for the full element list) and configure its outputs row by row to see this in action.