What "memory" means in digital logic
Every circuit covered so far either computes a result instantly from its current inputs (combinational logic) or stores a single bit (latches and flip-flops). Memory scales that single-bit idea up to thousands or billions of bits, organized so that any one of them can be read or written by supplying an address.
RAM: an array of latches
Random Access Memory is, conceptually, a grid of single-bit storage cells (in static RAM, literally a latch per bit) arranged in rows and columns. A decoder takes the address bits and activates exactly one row; the data on that row is then readable or writable through a shared set of data lines.
"Random access" means any address can be reached in the same amount of time, regardless of which address was accessed previously — unlike a shift register or tape, where reaching a far-away bit takes longer.
Reading and writing
A Write Enable line controls direction: when active, the decoded row's latches are set to whatever is on the data lines. When inactive, the decoded row's current contents are instead driven onto the data lines for reading. Only one row is ever selected at a time, which is exactly why the decoder from the previous article is the component that makes addressable memory possible at all.
ROM: permanently wired data
Read-Only Memory uses the same addressing principle — a decoder selects a row — but instead of latches, each cell is a fixed connection (present or absent) baked in at manufacturing time, or blown/programmed once in some variants. There is nothing to write: the same address always returns the same value, which makes ROM a perfect fit for data that must never change, like a bootloader or a fixed lookup table.
RAM vs ROM in practice
A real system uses both: ROM holds the startup code that runs before anything else is configured, and RAM holds working data and the program once loaded. Boolflow doesn't model a full memory array as a single block, but you can see the addressing principle directly: load a decoder example, and notice that the same decoder driving one of several latches is exactly how a tiny RAM is built from parts you already know.