A register is just flip-flops with a shared clock

A D flip-flop stores one bit; wire N of them to the same clock signal and you have an N-bit register that latches an entire word every clock edge. The only new ingredient a usable register needs is a Load enable input that decides whether the register accepts a new value this cycle or holds its current contents.

Building load enable from a multiplexer

The simplest way to add a load enable to a flip-flop with no built-in enable pin is a 2:1 multiplexer in front of its D input: when Load=1, the mux passes the new value through; when Load=0, it feeds the flip-flop's own current output back into itself, so the stored value stays put even though the clock keeps ticking. Boolflow's REG4 block is the flip-flop bank without that extra: it has four data inputs and a clock and nothing else, so it loads on every rising edge. To make it hold its value, put one MUX in front of each data input, with Q fed back into input A, the new data on input B and Load on the select pin S — four multiplexers, and the register keeps its contents whenever Load=0.

From one register to a register file

A CPU's register file is nothing more than several of these registers sharing one set of data input wires, with a decoder turning a binary register-address into exactly one active Load line — so a write only reaches the addressed register, while every other register's mux keeps feeding its own output back to itself. With just two registers, a single NOT gate does the job (Load0 = ¬Addr, Load1 = Addr); with more, Boolflow's Decoder 2:4 or Decoder 3:8 blocks scale the same idea up.

Try it yourself

Build two REG4 blocks in the circuit editor, each with four MUXes in front of its data inputs (Q back into A, one shared 4-bit data bus into B), drive the select pins of one register directly from a single address bit and those of the other through a NOT gate, and confirm that toggling the address bit routes a new value into only one register at a time.