Detecting a pattern in a stream of bits

The traffic light example advances entirely on its own; a sequence detector instead reacts to an external bit stream, one bit per clock, and needs to notice the exact moment a target pattern — say, the 3-bit sequence 1-0-1 — has just arrived, however it's interleaved with other bits before and after.

One state per 'how much progress so far'

Each state represents how much of the target sequence has been matched so far: S0 (no progress), S1 (matched a leading 1), S2 (matched 1-0), completing the match and heading back to S0 or S1 depending on what arrives next. Feeding a 0 while in S1 goes to S2; feeding a 1 while in S2 completes the match. Critically, matches are allowed to overlap: completing 1-0-1 from S2 lands back in S1, not S0, since that same final 1 could also be the start of the next match.

Why this needs a Mealy machine, not a Moore machine

The whole point is flagging the match the instant the deciding bit arrives, in the same clock cycle — exactly the same-cycle reactivity that defines a Mealy machine: output = f(state, input), not output = f(state) alone. A Moore version could only raise its output a full cycle after the pattern had already completed.

Try it yourself

Build the 2-bit state register and the next-state/output logic for the 1-0-1 detector in the circuit editor — three states fit comfortably in 2 bits — drive a bit stream through an INPUT switch one CLOCK edge at a time, and confirm the output pulses high the instant the third bit of a 1-0-1 pattern arrives, including overlapping matches like 1-0-1-0-1.