The synchronous design principle

A synchronous circuit drives every flip-flop from one shared clock signal, and only that clock signal. All state changes happen at the same instant, on the same edge, which is exactly what made synchronous counters immune to the ripple delay that affects their asynchronous counterparts. This single rule is what makes large digital systems with millions of flip-flops behave predictably.

Setup and hold time

Every flip-flop has two timing requirements around its clock edge: setup time, the minimum interval the data input must be stable before the edge, and hold time, the minimum interval it must remain stable after the edge. As long as data only changes outside this window, the flip-flop reliably captures a clean 0 or 1.

What happens when timing is violated: metastability

If the input changes inside the setup/hold window, the flip-flop's output can enter a metastable state — neither a clean 0 nor a clean 1, but some in-between voltage that eventually resolves to one or the other after an unpredictable extra delay. The real danger isn't the metastable voltage itself; it's that different gates reading that same output during the unresolved window can disagree about whether it was a 0 or a 1, corrupting downstream logic in a way that's very hard to reproduce or debug.

Crossing clock domains safely

Metastability becomes unavoidable whenever a signal crosses from one clock domain into another — for example, a button press (asynchronous to any clock) being read by a synchronous circuit. The standard fix is a synchronizer: two flip-flops in series, both clocked by the receiving domain. The first flip-flop may go metastable, but it has a full clock cycle to resolve before the second flip-flop samples it, making the probability of a downstream error astronomically small rather than zero.

Why this matters even outside chip design

Boolflow's simulation is idealized — signals settle instantly, so you won't see metastability in the editor itself. But the discipline still matters when you design a circuit: every CLOCK-driven block should read its inputs only from other synchronous logic, and any signal coming from outside (a manual INPUT toggle, in Boolflow's case) crossing into clocked logic is exactly the situation a real synchronizer exists to protect against. Load a flip-flop example and notice that every state change lines up with the same CLOCK edge — that alignment is the synchronous design principle in action.