Check

Checking a circuit for wiring errors

Most circuits that "do not work" are not wrong in their logic — they are wrong in their wiring. A gate input left unconnected, an output nobody reads, a wire that looks attached but ends one grid square short. These are invisible when you look at the drawing and obvious once something points at them.

This check walks the active layer and reports structural problems before you spend time debugging behaviour. It finds gate inputs with nothing driving them, outputs that lead nowhere, and elements stranded with no connections at all. It says nothing about whether your logic is correct — that is what the truth table and test cases are for — only about whether the circuit is completely and sensibly connected.

• An unconnected input is the most common cause of a “?” appearing in the truth table.
• A floating output is not always a fault — probes and spare gates are legitimate — so it is reported as information, not an error.
• Run the check before exporting: unconnected pins usually become undefined nets in Verilog and VHDL.

The check covers the active layer. In a multi-layer design, signals crossing through VIA elements are resolved by name, so verify each layer in turn.