A gate that does nothing, logically

A buffer (BUF) passes its input straight through unchanged: BUF(A) = A. That looks pointless on paper, but every real logic gate has a limited drive strength — the number of downstream gate inputs (its fan-out) it can reliably switch before the signal degrades into a slow, noisy transition instead of a clean edge.

Restoring signal strength

Route a signal through several passive stages, or fan it out to dozens of inputs, and its rise and fall times stretch out even though its logical value never changes. A buffer re-drives the signal at full strength, resetting the fan-out budget and sharpening the edge, without touching the 0s and 1s at all. An inverting buffer (INVBUF) does the same job while also flipping the value — useful when a design needs one more inversion anyway.

Where buffering matters most: clock trees

A clock signal typically fans out to every flip-flop and register in a design — far more loads than one gate could drive directly. Real chips solve this with a clock tree: a hierarchy of buffers, each driving only a handful of the next stage, so every flip-flop receives a strong, sharp clock edge at (ideally) the same instant.

Try it yourself

Chain several BUF elements after a signal that already fans out to many gates in the circuit editor. Boolflow's simulation is idealized, so you won't see the signal actually degrade, but the structure — one strong driver feeding many loads through intermediate buffers — is exactly what real fan-out limits force onto a physical design. See the Help reference for BUF and INVBUF's exact behaviour.