A loop is a memory
A gate has no memory: its output is a function of its inputs right now. Memory appears the moment you feed an output back into an input. Take two NOR gates and cross-couple them, so that Q = NOR(R, ~Q) and ~Q = NOR(S, Q). Each output now depends on the other, and through it on its own past.
Set, hold, reset
A NOR gate outputs 0 as soon as any input is 1, whatever the other input is. That single fact runs the whole latch. Raise S: the lower gate sees a 1, so ~Q becomes 0. The upper gate now sees R = 0 and ~Q = 0, so Q becomes 1. Lower S again and nothing moves: the lower gate sees S = 0 and Q = 1, so ~Q stays 0, which keeps Q at 1. The latch is holding a 1 with no input asking it to.
Reset is the mirror image: raise R and Q falls to 0, which lets ~Q rise to 1 and stay there when R is released.
- S = 0, R = 0: hold whatever was stored.
- S = 1, R = 0: set, so Q = 1 and ~Q = 0.
- S = 0, R = 1: reset, so Q = 0 and ~Q = 1.
- S = 1, R = 1: forbidden, both outputs are 0.
What Boolflow shows at power-up
Boolflow computes with three values per wire: 0, 1 and unknown. A latch that has just been switched on with S = R = 0 is genuinely in an unknown state, and the editor shows Q and ~Q as ?. The first pulse on S or R settles it, because a NOR with a 1 on one input is decided even while its other input is still unknown. After that the circuit remembers: each tick starts from the wire values the previous tick left, which is exactly how the loop holds its bit.
The forbidden input
Hold S = R = 1 and both gates see a 1, so both outputs are 0. That is not a stored bit, since Q and ~Q should be opposites. The trouble comes when both inputs are released together. Each gate now sees two zeros and wants to output 1; once both do, each sees a 1 and wants to output 0; and so on forever. In real silicon one gate is always slightly faster and wins the race, but nobody can tell in advance which, and that is the root of metastability. Boolflow updates all the gates of a round together, so the tie never breaks: the two outputs are shown as ? and the status bar says the circuit does not settle. A proper set or reset afterwards recovers it. In the editor, two separate switches are released one after the other, and the latch then simply lands in a definite state; to release both in the same instant, wire one switch to both S and R.
From latch to flip-flop
Swap the NORs for NANDs and the inputs become active low: a 0 on S sets, a 0 on R resets. Put two more NANDs and an inverter in front and you have a gated D latch, which follows D while E = 1 and holds while E = 0. Chain two of those with opposite enables and the output can change only at the moment the clock rises: a master-slave D flip-flop built from nothing but gates. Boolflow has all three as examples: the NOR latch, the gated D latch and the gate-level flip-flop.
Try it yourself
Open the NOR latch and click S, then release it: Q stays at 1. Click R to clear it. Then wire one switch to both S and R, switch it on and off and watch the status bar. Finally try the flip-flop: switch CLK up and down while changing D, and see that Q only follows D on the rising edge.