A table of expected rows
The Test Cases page lets you write expected behaviour as a plain text table — one column per input and output, one row per combination you want to check, using 0, 1, or x for "don't care." Unless the table contains a clock pulse (more on that below), each row runs through its own independent simulation: the listed inputs are driven, the listed outputs are compared, and any row that doesn't match is flagged immediately.
This is exactly a hand-written truth table
A test-case table is nothing more than the truth table you expect your circuit to produce, written down in advance instead of generated automatically afterward — useful the moment a circuit gets big enough that eyeballing the auto-generated truth table stops being a reliable way to catch a mistake.
Testing clocked circuits with C
Put a C in an input column and that signal is pulsed: it goes 0, then 1, then back to 0, and the outputs are checked once the circuit has settled. A table that contains a C stops being a list of independent rows and becomes a sequence. It runs from the top starting from power-up, with every flip-flop and register at 0, state carries from one row to the next, and an x in an input column keeps whatever that input held in the row before.
A 4-bit counter becomes a column of C with the count you expect after each pulse: after the first pulse Q0…Q3 read 1 0 0 0, after the second 0 1 0 0, and so on. A toggle flip-flop (a D flip-flop whose D is driven by NOT Q) is just four rows of C expecting 1, 0, 1, 0.
Two limits are worth knowing. Time between pulses is not modelled: a pulse is an instant 0, 1, 0, not a duration, so the table cannot test setup or hold times. And the test runs on its own copy of the circuit's state, so running a table never disturbs the counters you are watching in the editor.
Try it yourself
Write a small test-case table for a half adder in the circuit editor — four rows covering every combination of A and B — confirm it passes, then deliberately swap two output columns to see how the page reports the mismatch.
Then do the same for a clocked circuit: wire a D flip-flop's Q output through a NOT gate back to its own D input, put an INPUT labelled CLK on its clock pin and an OUTPUT labelled Q on its output, and write the table "CLK | Q" with four rows "C | 1", "C | 0", "C | 1", "C | 0".