Export Verilog

Exporting a circuit to Verilog

Verilog is the hardware description language most FPGA and ASIC toolchains speak. Exporting your schematic to Verilog turns a drawing into something a synthesis tool can actually build: the gates you placed become a module with named ports and a set of continuous assignments.

Boolflow reads the active layer, walks the graph from inputs to outputs, and emits one assignment per gate. Every INPUT element becomes an input port, every OUTPUT an output port, and the wires between them become named nets. The result is plain structural Verilog with no vendor-specific constructs, so it compiles under Icarus Verilog, Verilator, Vivado and Quartus alike.

• Module name is configurable — it becomes both the file name and the identifier you instantiate.
• The optional testbench generates a stimulus module that sweeps the inputs, so you can simulate immediately without writing one by hand.
• Elements with no Verilog equivalent are reported rather than silently dropped.

// Generated by BoolFlow
module half_adder (
  input  A, B,
  output S, C
);
  assign S = A ^ B;
  assign C = A & B;
endmodule

Combinational circuits translate directly. Clocked elements are emitted where an equivalent exists, and anything unsupported is listed above the code so you know what to add by hand.