A function, not a simulator

Where the HDL exporters produce a hardware description meant for a synthesis tool, the C++ exporter produces something meant to run directly: a single pure function — bool boolflow(bool in_0, bool in_1, ...), or one returning a small Outputs struct when there's more than one output — computed by topologically sorting the circuit's combinational graph so every gate evaluates after everything feeding it. Drop that function straight into another C++ program and it behaves exactly like the circuit it came from.

Standalone too, via a generated main()

Boolflow can also emit a complete, runnable main() around that same function — one that exhaustively drives every input combination and prints the resulting truth table — useful for confirming the exported code matches the circuit before ever integrating it anywhere, with no second tool required.

PLM blocks translate too

Unlike the HDL exporters, the C++ exporter also understands PLM blocks: whatever boolean formula you typed into a PLM's configuration gets translated directly into an equivalent C++ expression inside the generated function, rather than being skipped as unsupported.

The honest limitation: no clock, no state

The C++ exporter shares the same combinational-only restriction as the HDL exporters — there's no class, no member variables, no step() or tick() method, nothing that remembers a previous cycle. A circuit built from flip-flops, REG4, SHIFT4, or any counter exports with those elements skipped, exactly as in Verilog and VHDL; the real differentiator here is being a plain, embeddable function for combinational logic, not a full software model of a sequential design.