One flat module, with named ports

Both exporters read whichever layer is currently open and emit exactly one Verilog module (or one VHDL entity/architecture pair) for it — there's no multi-module hierarchy, even if your design spans several layers; each layer exports as its own independent block. Every INPUT and OUTPUT node becomes a port, and if you gave the node a name, that name is used — cleaned up into a legal identifier, kept unique, and replaced by a positional fallback (in_0, in_1, out_0, … in placement order) when it would clash with a reserved word or contain nothing but non-Latin characters. A free-standing LABEL element is only an on-screen annotation and never reaches the generated code.

Combinational logic only

The Verilog exporter emits nothing but assign statements; the VHDL exporter emits nothing but concurrent signal assignments inside one architecture. Neither ever produces a clocked process — no always @(posedge clk), no VHDL process(clk) — so every stateful element (flip-flops, REG4, SHIFT4, CNT4, and the rest) is skipped entirely, marked with an explicit 'unsupported' note in the output rather than silently dropped.

Bits, not buses

Neither exporter has a concept of a multi-bit vector. A 4-bit block like ADD4 or CMP4 is exploded into four separate 1-bit signals wired together — bit concatenation in Verilog, explicit STD_LOGIC_VECTOR/UNSIGNED helper signals in VHDL, which gives the VHDL output a slightly more idiomatic feel for arithmetic even though the underlying model is identical in both.

Try it yourself

Build a purely combinational circuit — a 4-bit comparator, say — in the circuit editor, export it to both Verilog and VHDL, and compare the two outputs side by side to see the same one-bit-at-a-time structure expressed in each language's own idioms.