Export VHDL

Exporting a circuit to VHDL

VHDL describes the same hardware as Verilog but with a stricter, more verbose syntax, and it remains the standard in European industry, aerospace and much of academia. If your course or your employer requires VHDL, this export saves you transcribing a schematic by hand.

Boolflow emits a complete design unit: the IEEE library clause, an entity that declares one port per INPUT and OUTPUT element, and a behavioural architecture containing one signal assignment per gate. Types are std_logic throughout, which is what synthesis tools expect and what lets you wire the result into a larger design without conversion functions.

• The entity name is configurable and must match the file name in most VHDL toolchains — Boolflow keeps them in step.
• The optional testbench instantiates the entity and drives its inputs, ready for GHDL or ModelSim.
• Unsupported elements are listed explicitly instead of producing code that will not compile.

-- Generated by BoolFlow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adder is
  port ( A, B : in  STD_LOGIC;
         S, C : out STD_LOGIC );
end half_adder;

architecture Behavioral of half_adder is
begin
  S <= A xor B;
  C <= A and B;
end Behavioral;

VHDL is case-insensitive but strict about declaration order and semicolons. The generated file is complete and self-contained — you can hand it to a synthesiser without editing.